The SUS Hardware Description Language

A return to RTL for high-performance Hardware Designs

🔽 How to install SUS 📄 Documentation

Why SUS?

SUS stands out compared to other HDLs like Verilog or VHDL due to its:

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Latency Counting

Timing and pipelining is easier to reason about because the compiler keeps track of them.

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Made for tinkering

The compiler keeps track of many aspects of your hardware design, and displays them in the editor.

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Full Control

If you can draw your design as synchronous logic, you can represent it in SUS.

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Powerful Metaprogramming

SUS supports compile-time code execution to

More Examples

Core Philosophy

SUS is meant to be a direct competitor to Synthesizeable Verilog and VHDL. Its main goal is to be an intuitive and thin syntax for building netlists, such that traditional synthesis tools can still be used to analyze the resulting hardware. SUS shall impose no paradigm on the hardware designer, such as requiring specific communication protocols or iteration constructs. In other words, SUS is not there to abstract away complexity, but rather to make the inherent complexity of hardware design more manageable.

The one restriction SUS does impose over Verilog and VHDL is that it requires the hardware to be synchronous over one or more clocks. Asynchronous hardware is therefore unrepresentable making SUS less suitable for ASIC development.

  • Generative Variables and Types: Can be freely combined, sidestepping any "Dependent Types" headaches.
  • Easy Pipelining: Achieved through an orthogonal construct called "Latency Counting" that doesn't interfere with other features.
  • Separation of Pipelines: Using interfaces to prevent crossing signals without logical relationship.
  • A direct 1-to-1 mapping from code to netlist
  • Hardware domain separation with explicit crossing primitives
  • A built-in syntax for pipelining that does not impose structural constraints
  • In-IDE compilation errors & warnings
  • Metaprogramming for hardware generation
  • Type safety with Bounded Integers
  • Multi-Clock modules
  • Formal Verification Integration
  • Syntactic sugar for common constructs like valid signals, resets and submodule communication
  • Moving some timing constraints to the source file
  • Provide abstractions for handshake protocols (like AXI)
  • Runtime iteration constructs
  • Automatic pipelining & retiming

Learn SUS in 40 Minutes

Watch an introductory video covering the basics of the language.

Join the SUS Community

Connect with us on our platforms like GitHub or Discord.