memory

Modules

ROM #(T, int DEPTH, T[DEPTH] DATA)

module ROM #(T, int DEPTH, T[DEPTH] DATA) {
    action read : int #(FROM: 0, TO: DEPTH) index'0 -> T output_data'1
}

RAM #(T, int DEPTH)

module RAM #(T, int DEPTH) {
   domain w_dom
    action write'0 : int#(FROM: 0, TO: DEPTH) write_addr'0, T write_data'0
   domain r_dom
    action read'0 : int#(FROM: 0, TO: DEPTH) read_addr'0 -> T read_data'1
}

Simple Dual Port RAM Module.

The write port and read port are fully independent. The RAM has a write-after-read policy, so when writing and reading to the same address in the same cycle, the old value is returned.

DPRAM #(T, int DEPTH)

module DPRAM #(T, int DEPTH) {
   domain dom_a
    action write_a'0 : int#(FROM: 0, TO: DEPTH) write_addr_a'0, T write_data_a'0
    action read_a'0 : int#(FROM: 0, TO: DEPTH) read_addr_a'0 -> T read_data_a'1
   domain dom_b
    action write_b'0 : int#(FROM: 0, TO: DEPTH) write_addr_b'0, T write_data_b'0
    action read_b'0 : int#(FROM: 0, TO: DEPTH) read_addr_b'0 -> T read_data_b'1
}

True Dual Port RAM Module.

Ports a and b are fully independent, and each can be used to perform either a read or a write each cycle.

It is an error to call both write_a and read_a at the same time, as well as write_b and read_b.

When writing with both write_a and write_b to the same address at the same time, write_b takes prescedence.

RAM_Unbalanced #(ElemT, int DEPTH, int WRITE_SIZE, int READ_SIZE)

module RAM_Unbalanced #(ElemT, int DEPTH, int WRITE_SIZE, int READ_SIZE) {
   domain w_dom
    action write'0 : int#(FROM: 0, TO: DEPTH / WRITE_SIZE) write_addr'0, ElemT[WRITE_SIZE] write_data'0
   domain r_dom
    action read'0 : int#(FROM: 0, TO: DEPTH / READ_SIZE) read_addr'0 -> ElemT[READ_SIZE] read_data'1
}