Introduction
User Guide
1.
Installation
2.
Learning SUS
2.1.
Changelog since Talk
philosophy
3.
Compiletime and Runtime
4.
Control Flow
5.
Design Decisions
6.
Instantiation
7.
Interfaces
8.
Latency
9.
Library
10.
Optimization
11.
State
12.
State vs Latency
13.
The Trouble with Parsing Templates
14.
Tensions
15.
Tree Sitter
16.
Types
17.
Core Philosophy
17.1.
What SUS gives you
17.2.
Planned
17.3.
What SUS does not do
17.4.
SUS Code Examples
18.
Comparison to Other HDLs
19.
Main Features through examples
19.1.
Pipelining through Latency Counting
19.2.
FIZZ-BUZZ Lookup Table using Generative Code
19.3.
(Clock-) Domains for separating out logically distinct pipelines
20.
Roadmap
20.1.
Major Milestones
20.2.
Language Features
20.3.
Performance, Linking and Name Resolution
20.4.
Safety
20.5.
Typing & Inference
20.6.
Latency Counting
20.7.
LSP
20.8.
Code Generation
20.9.
Fun projects to do in SUS
20.10.
Safety through Interface Asserts (PDL-style asserts)
20.11.
Simulation
21.
Architecture
Long Term Strategy
Light (default)
Rust
Coal
Navy
Ayu
Code Generation
Expression Flattening
Can Generate Verilog for Multiply-Add pipeline
Can Generate Verilog for Blur2 filter
Can Generate Verilog for FIFO
Multi-Clock Modules
Clock Tracking for SubModules